3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect

EasyChair Preprint 12223

Abstract

This paper presents a flash, Time Domain ADC with T/H amplifier, Voltage Controlled Delay Line and Time to Digital Converter. The design is operating at 3.125GS/s with 4.9 ENOB and a Walden figure of merit of 109fJ/Conversion. Automatic calibration means are provided as well. For measurements purposes, an integrated memory is provided. It consumes 16.2mW from a 1V supply. It was realized in the 45nm PDSOI from Global Foundries.

Keyphrases: Backplane interconnect, Gigabit Radio, Sampler, Time-Domain ADC, Track and Hold, mm-waves

@booklet{EasyChair:12223,
  author    = {Solomon Micheal Serunjogi and Mihai Sanduleanu},
  title     = {3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect},
  howpublished = {EasyChair Preprint 12223},
  year      = {EasyChair, 2024}}