Nanoscale FinFET Based 6T SRAM Cell Design Analysis for Leakage Power Reduction

EasyChair Preprint no. 6220

Abstract

At nanoscale technology nodes, various parameter variations and short channel effects greatly impact the semiconductor devices. The innovative and holistic circuit-level methodology is required to trade between power, area, and robustness while maintaining adequate manufacturing yield. FinFET based design as an alternative solution to the bulk devices for reducing short channel effects and leakage power. Many approaches have been earlier implemented to minimize the leakage power but were only able to minimize the fraction of leakage power. I have proposed a Hybrid technique and implemented it on a FinFET based 6T SRAM cell. It reduces the power dissipation in standby mode as leakage current is minimized and without charging the area penalty. Compared to the conventional FinFET, we achieved a reduction in leakage current and static power dissipation at 25.59% and 31.29% respectively at a constant 45nm channel length on Cadence virtuoso at room temperature.

Keyphrases: AVL, Hybrid, leakage current, leakage power, MTCMOS, SRAM

@Booklet{EasyChair:6220,
  author = {Vishal Gupta},
  title = {Nanoscale FinFET Based 6T SRAM Cell Design Analysis for Leakage Power Reduction},
  howpublished = {EasyChair Preprint no. 6220},

  year = {EasyChair, 2021}}