Timing Analysis in Pid Controller Using Data and Clock Load

EasyChair Preprint no. 7833

Abstract

Proportional-Integral-Derivative (PID) control is the most commonly used control algorithm in industries and has been universally accepted in industrial control, like for industries such as chemical, petrochemical, robotics etc. The popularity of PID controllers is due to the fact that they are low cost, easy to maintain and also gives robust performance in a wide range of operating conditions. In order to improve the performance of the PID controller, Razor flip flops are used to detect and correct timing errors on critical path. In this proposed work, novel Flip Flop called Razor Clock Gated Flip Flop (RCGFF) by using Pulse-Triggered Flip-Flop is introduced. The designed circuit is used to reduce the timing error and increasing the robustness in integrated sequential circuits. RCGFF is mainly contributing to high-precision, high-speed, power reduction in static and average power consumption in PID controller. This technique is suitable for low power and data communication in PID controller. Results are validated by simulations, 74% of power reduction occurs compare to conventional design, by using IBM 130 nm with 1.8 supply voltage. The proposed RCGFF is compared with previous work in terms of power consumption, Power Delay Product (PDP), time delay and area.

Keyphrases: and Timing error, Proportional-Integral-Derivative (PID) controller Pulse-Triggered Flip-Flop, Razor

@Booklet{EasyChair:7833,
  author = {S Saravanakumar and V Rukkumani},
  title = {Timing Analysis in Pid Controller Using Data and Clock Load},
  howpublished = {EasyChair Preprint no. 7833},

  year = {EasyChair, 2022}}